Integrated circuits generally include transistors connected by numerous levels of interconnect routing in the form of electrical interconnects embedded within a dielectric substrate. Each level of interconnect routing is separated from immediately adjacent levels by dielectric material, referred to as interlayer dielectric (ILD). The ILD generally includes an oxide layer, such as silicon dioxide formed from tetraethyl orthosilicate (TEOS), and may include one or more additional layers of dielectric material such as low-k or ultra-low k (ULK) material. Adjacent levels of interconnect routing may be embedded in distinct layers of ILD and configured to ensure that dielectric material separates adjacent interconnect routings.
As scaling of integrated circuits increases, aspect ratios of height to width of embedded electrical interconnects in interconnect routing have been maximized to minimize spacing between embedded electrical interconnects. However, minimized spacing between the embedded electrical interconnects leads to device reliability concerns attributable to various phenomena. One particular phenomenon that affects device reliability is time dependent dielectric breakdown (TDDB), which results from migration of metal ions from the embedded electrical interconnects into an interface between adjacent levels of the interconnect routing. TDDB is often exacerbated with decreased spacing between embedded electrical interconnects in interconnect routings. To inhibit TDDB, efforts have been made to recess embedded electrical interconnects within the ILD to offset embedded electrical interconnect surfaces from planes of interfaces between adjacent levels and to effectively form a barrier to flow of metal ions into the interfaces.
To further inhibit TDDB attributable to migration of metal ions from the embedded electrical interconnects into the interface between adjacent levels of the interconnect routing, a barrier layer, such as tantalum nitride, is often formed between the electrically-conductive material and the dielectric and oxide layers. A liner layer, such as tantalum, may be formed between the barrier layer and the electrically-conductive material to further assist as a barrier to flow of metal ions into the interface. Recessing of the barrier layer and the liner layer within the substrate is desirable to promote electrical insulation of the embedded electrical interconnects and to further minimize TDDB. However, there has been difficulty with employing the above techniques effectively due to uneven topography, reduction in the volume of ILD separating interconnect routing, and break down of the oxide layer.
Accordingly, it is desirable to provide methods for fabricating integrated circuits that recess embedded electrical interconnects and barrier layers within substrates while minimizing etching of oxide layers in the substrates. Further, it is desirable to provide methods for fabricating integrated circuits that provide improved techniques for recessing embedded electrical interconnects and adjacent barrier layers. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.